The present invention relates in general to transistor structures and to methods for their fabrication, and in particular to an NPN double heterostructure bipolar transistor (DHBT) fabricated on a gallium arsenide (GaAs) substrate and having an indium gallium arsenide nitride (InGaAsN) base region.
The growing market of portable electronic devices including cellular telephones demands high-performance electronic circuitry having minimal power dissipation to prolong battery life. Reducing the power dissipation of electronic circuitry requires transistors that operate with a small voltage swing. One approach that has been used to form heterostructure bipolar transistors (HBTs) having a low voltage swing has been to form a GaAs transistor having a strained indium gallium arsenide (InGaAs) base region, with the substrate being GaAs. A disadvantage of this approach is that the amount of indium that can be incorporated into the base region to lower the voltage swing is limited due to the formation of misfit dislocations as the InGaAs base becomes increasingly strained relative to the GaAs substrate.
Another approach that has been used is to form the HBT with a lattice-matched InGaAs base on an indium phosphide (InP) substrate so that more indium can be incorporated into the base region without the formation of misfit dislocations. This is the approach that is currently used for fabricating low-power HBTs. However, the unavailability of large-size ( greater than 4 inches in diameter) InP substrates and the relatively high cost of InP substrates compared to GaAs substrates makes production costs relatively high when using this approach so that its use has not become widespread in the consumer marketplace.
The present invention relates to an NPN double-heterostructure bipolar transistor (DHBT) which is based on the use of a p-doped indium gallium arsenide nitride (InGaAsN) layer for the base region. The collector region of the transistor can be formed of GaAs or InGaAsN; and the emitter region can be formed of indium gallium phosphide (InGaP), GaAs or aluminum gallium arsenide (AlGaAs).
An advantage of the present invention is that the transistor can be fabricated on GaAs substrates which are available in large sizes (4 to 6 inches in diameter) and at lower cost than alternative substrates (e.g. InP), thereby potentially reducing fabrication costs, and also allowing fabrication in commercial GaAs foundries.
Another advantage of the present invention is that the use of InGaAsN for the p-type base region of the NPN transistor can provide a reduced voltage swing, thereby reducing power dissipation in the transistor.
A further advantage of the present invention is that the structure of the transistor can be made substantially strain-free with the InGaAsN base region substantially lattice-matched to the GaAs substrate.
Yet another advantage of the present invention is that the transistor can operate up to very high frequencies on the order of 50 GHz or more.
These and other advantages of the method of the present invention will become evident to those skilled in the art.
The present invention relates to an NPN double-heterojunction bipolar transistor (DHBT) formed on a gallium arsenide (GaAs) substrate (e.g. a semi-insulating GaAs substrate). The transistor comprises a base region which further comprises a layer of p-type-doped indium gallium arsenide nitride (InGaAsN). An emitter region is located on one side of the base region and further comprises a layer of a first n-type-doped semiconductor having a bandgap energy greater than the bandgap energy of the InGaAsN base region. A collector region is located on the other side of the InGaAsN base region and further comprises a layer of a second n-type-doped semiconductor having a bandgap energy greater than or equal to the bandgap energy of the InGaAsN base region. Electrodes are provided on the NPN transistor to form separate electrical connections to each of the collector, emitter and base regions. The first n-type-doped semiconductor forming the emitter region can comprise GaAs, aluminum gallium arsenide (AlGaAs), or indium gallium phosphide (InGaP); and the second n-type-doped semiconductor forming the collector region can comprise GaAs or InGaAsN.
The InGaAsN base region comprises the semiconductor alloy composition InxGa1xe2x88x92xAs1xe2x88x92yNy with 0 less than xxe2x89xa60.1 and with 0 less than yxe2x89xa60.03. Alternately, the base region can comprise a compositionally-graded InxGa1xe2x88x92xAs1xe2x88x92yNy layer having y less than 0.01 near the emitter region and a larger value of 0.01xe2x89xa6yxe2x89xa60.03 near the collector region. The p-type doping of the InGaAsN base region can also be varied in concentration across the base region with a higher level of the p-type-doping (e.g. 1019 cmxe2x88x923) being provided near the emitter region and with a lower level of the p-type doping (e.g. 1017 cmxe2x88x923) being provided near the collector region.
The NPN double-heterojunction bipolar transistor can further include a first bandgap-smoothing transition region (also termed herein a first transition region or a first transition layer) located between the base and collector regions. The first bandgap-smoothing transition region can comprise a layer of compositionally-graded indium gallium arsenide (InGaAs) or InGaAsN with n-type doping. In the case of an InGaAs first transition region, the semiconductor alloy composition of the InGaas can comprise InxGa1xe2x88x92xAs with x varying across the transition region from a low value of x (e.g. x less than 0.1) near the collector region to a higher value of x (e.g. 0.1xe2x89xa6xxe2x89xa60.4) near the base region. In the case of an InGaAsN first transition region, the semiconductor alloy composition of the InGaAsN can comprise InxGa1xe2x88x92xAs1xe2x88x92yNy with x and y varying (i.e. stepped or graded in composition) from low values of x and y (e.g. x=0 and y=0) near the collector region to higher values of x and y (e.g. xxe2x89xa70.03 and yxe2x89xa70.01) near the base region. By appropriate epitaxial growth of the InxGa1xe2x88x92xAs1xe2x88x92yNy transition region (i.e. with x=3y), the first transition region can be formed substantially strain-free. The first transition region can further comprise a delta-doped portion (i.e. a sheet of n-type doping of, for example, 5xc3x971012 cmxe2x88x922).
In some embodiments of the present invention, a second bandgap-smoothing transition region can be provided in the transistor between the base and emitter regions. This second bandgap-smoothing transition region with n-type doping can further include a delta-doped portion (e.g. a sheet of n-type doping of, for example, 5xc3x971012 cmxe2x88x922). When the emitter region comprises InGaP or AlGaAs, the second bandgap-smoothing transition region can comprise, for example, AlxGa1xe2x88x92xAs with x varying across the second bandgap-smoothing transition region from x=0 near the base region to a value of x that provides a bandgap energy substantially equal to that of the InGaP or AlGaAs emitter region.
A passivation layer can be provided on the transistor overlying exposed portions of the collector, emitter and base regions of the transistor to improve performance by reducing effects due to surface recombination. The passivation layer can comprise, for example, a layer of silicon oxynitride.
The present invention also relates to an NPN double-heterojunction bipolar transistor formed on a GaAs substrate and comprising a plurality of semiconductor layers epitaxially grown on the substrate, including a layer of GaAs with n-type doping forming a collector region of the transistor, a layer of indium gallium phosphide (InGaP) with n-type doping forming an emitter region of the transistor, and a layer of indium gallium arsenide nitride (InGaAsN) with p-type doping forming a base region which is sandwiched between the collector and emitter regions. Electrodes are provided on the transistor to separately contact each of the collector, emitter and base regions.
The collector region can include a relatively low n-type doping level (e.g. 1015-1016 cmxe2x88x923) near the base region, and an increased doping level (e.g. 1018-1019 cmxe2x88x923) away from the base region (i.e. to form a sub-collector region). The emitter region can insert further include a delta-doped portion (e.g. a sheet of doping of, for example, 5xc3x971012 cmxe2x88x922). The layer of InGaAsN forming the base region can be p-type doped, for example, in the range of 1018 to 1020 cmxe2x88x923.
The InGaAsN layer forming the base region 16 comprises InxGa1xe2x88x92xAs1xe2x88x92yNy with an indium composition, x, given by 0 less than xxe2x89xa60.1 and a nitrogen composition, y, given by 0 less than yxe2x89xa60.03. To form a substantially-strain-free base region, the indium composition, x, is about three times the nitrogen composition, y. Thus, for example, when y=0.01 in the InxGa1xe2x88x92xAs1xe2x88x92yNy base region, then x=0.03. In other embodiments of the present invention, the base region of the transistor can comprise InxGa1xe2x88x92xAs1xe2x88x92yNy with x and y being varied (i.e. stepped or graded in composition) across the base region to provide a smaller value of y (e.g. y less than 0.01) near the emitter region and a larger value of y (e.g. 0.01xe2x89xa6yxe2x89xa60.03) near the collector region, thereby grading the semiconductor alloy composition of the base region. The p-type doping of the InGaAsN layer forming the base region can also be varied across the base region from a higher level of the p-type-doping on a side of the base region proximate to the emitter region to a lower level of the p-type doping being on the opposite side of the base region proximate to the collector region.
This transistor structure preferably further includes a first bandgap-smoothing transition region located between the base and collector regions. The first transition region can comprise a layer of compositionally-graded indium gallium arsenide (InGaAs) or InGaAsN. The first transition region can further comprise a delta-doped portion (e.g. a sheet of n-type doping of, for example, 5xc3x971012 cmxe2x88x922). A second bandgap-smoothing transition region (e.g. comprising a layer of compositionally-varying AlxGa1xe2x88x92x As with, for example, x=0 near the base region and graded in composition to xxe2x89xa60.3 near the emitter region can optionally be provided between the base and emitter regions. The second bandgap-smoothing transition region can further include a delta-doped portion.
The NPN transistor of the present invention can be formed with a mesa structure so that each of the collector, emitter and base regions can be independently contacted. To reduce surface recombination which can be detrimental to device performance, a passivation layer can be provided over exposed portions of the collector, emitter and base regions of the transistor. The passivation layer can comprise, for example, silicon oxynitride which can be deposited using a plasma (e.g. an electron-cyclotron resonance plasma).
The present invention further relates to an NPN double-heterojunction bipolar transistor that comprises a plurality of semiconductor layers epitaxially grown on a GaAs substrate, with the semiconductor layers being patterned to form a mesa structure for the transistor. The semiconductor layers in this embodiment of the present invention include a layer of n-type-doped GaAs grown on the substrate to form the collector region of the transistor; a first bandgap-smoothing transition region comprising a layer of n-type-doped compositionally-graded InGaAs or InGaAsN overlying the collector region; a layer of p-type-doped InGaAsN overlying the transition region to form the base region of the transistor; a layer of n-type-doped InGaP above the base region to form an emitter region of the transistor; a layer of n-type-doped GaAs forming a super-emitter region above the InGaP layer; and an n-type-doped InGaAs cap layer above the super-emitter region. Electrodes are provided to each of the collector, emitter and base regions of the transistor, with the electrical connection to the emitter region being formed on the cap layer. For high-speed operation, the substrate preferably comprises semi-insulating (S.I.) GaAs.
The first transition region in this embodiment of the present invention can further include a delta-doped portion (also termed herein a xcex4-doped portion) to improve electron flow and to reduce a base-to-emitter voltage swing required to operate the transistor. Additionally, the emitter region can also include a delta-doped portion. Finally, the transistor can include a passivation layer (e.g. comprising silicon oxynitride) covering exposed portions of the collector, emitter and base regions of the transistor which can be formed as a mesa structure (e.g. a triple-mesa structure).
Additionally, the present invention relates to a method for forming an NPN double-heterojunction bipolar transistor, comprising steps for providing a GaAs substrate having a plurality of semiconductor layers epitaxially grown thereon; defining a structure for the transistor; and electrically contacting the collector, emitter and base regions. The semiconductor layers used to form the transistor include a layer of n-type-doped GaAs forming the collector region, a layer of n-type-doped InGaP forming the emitter region; and a layer of p-type-doped InGaAsN forming the base region, with the base region being sandwiched between the collector and emitter regions.
As described previously, the substrate can comprise a semi-insulating GaAs substrate; a first n-type-doped semiconductor layer (e.g. GaAs or InGaAsN) can be epitaxially grown to form the collector region of the transistor; and a second n-type-doped semiconductor layer (e.g. InGaP, GaAs, or AlGaAs) can be epitaxially grown to form the emitter region of the transistor. The base region is formed by epitaxially growing a layer of p-type-doped InGaAsN sandwiched between the collector and emitter regions.
The epitaxially-grown semiconductor layers can further include a first bandgap-smoothing transition region (e.g. comprising compositionally-graded InGaAs or InGaAsN) located between the collector and base regions, with the first transition region optionally including a delta-doped portion. A delta-doped portion can also be provided in the emitter region, or alternately in a second bandgap-smoothing transition region (e.g. comprising compositionally-graded AlGaAs) which can be epitaxially grown between the emitter and base regions.
The step for defining the structure for the NPN transistor can comprise patterning the semiconductor layers to form a mesa structure, or alternately ion implanting the semiconductor layers to form a planar structure. The mesa structure can be formed, for example, by selectively etching the semiconductor layers with a wet etchant comprising phosphoric acid, hydrogen peroxide and water. The NPN transistor with its mesa structure can be passivated for improved performance by forming a passivation layer overlying exposed portions of the collector, emitter and base regions (e.g. by depositing a layer of silicon oxynitride over these exposed portions). The step for electrically contacting the collector, emitter and base regions can comprise forming a germanium/gold/nickel/gold contact or a palladium/germanium/gold contact for the collector, a tungsten silicide or a palladium/germanium/gold for the emitter, and a platinum/titanium/platinum/gold contact for the base.
Finally, the present invention relates to a method for forming an NPN double-heterojunction bipolar transistor on a GaAs substrate, comprising steps for epitaxially growing a plurality of semiconductor layers on the GaAs substrate including a first n-type-doped semiconductor layer (e.g. comprising GaAs or InGaAsN) forming a collector region of the transistor, a second n-type-doped semiconductor layer (e.g. comprising InGaP, GaAs or AlGaAs) forming an emitter region of the transistor, and a layer of p-type-doped InGaAsN forming the base region, with the base region being sandwiched between the collector and emitter regions; defining a structure for the transistor; and electrically contacting the collector, emitter and base regions.
The step for epitaxially growing the semiconductor layers preferably comprises epitaxially growing the semiconductor layers by metalorganic chemical vapor deposition (MOCVD), and can further include a step for epitaxially growing a first bandgap-smoothing transition region between the collector and base regions. The step for epitaxially growing the first transition region can comprise epitaxially growing a layer of InGaAs between the collector and base regions, with the InGaAs layer having the semiconductor alloy composition InxGa1xe2x88x92xAs with an indium composition, x, being graded from x less than 0.1 near the collector region to 0.1xe2x89xa6xxe2x89xa60.4 near the base region. Alternately, the step for epitaxially growing the first transition region can comprise epitaxially growing a layer of compositionally-graded InxGa1xe2x88x92xAs1xe2x88x92yNy with x and y varying across the first transition region from low values of x and y (e.g. x=0 and y=0) near the collector to higher values of x and y (e.g. xxe2x89xa70.03 and yxe2x89xa70.01) near the base region. Under appropriate growth conditions (i.e. with x=3y), the compositionally-graded InxGa1xe2x88x92xAs1xe2x88x92yNy first transition region can be formed substantially strain-free.
The process of growing the first transition region can also include delta-doping a portion thereof for further bandgap smoothing (i.e. for facilitating the flow of carriers across the device). Delta-doping can also be included in the epitaxial growth of the emitter region, or in an optional second bandgap-smoothing transition region located between the base and emitter regions. The second bandgap-smoothing transition region can be formed, for example, by epitaxially growing a layer of AlxGa1xe2x88x92xAs with x=0 near the base and with xxe2x89xa60.3 near the emitter region.
As described previously, the NPN transistor of the present invention can be defined by etching the semiconductor layers to form a mesa structure. This etching step can be performed using a wet etchant comprising phosphoric acid, hydrogen peroxide and water. After the transistor structure has been defined, a further step can be provided for passivating the transistor by depositing a layer of silicon oxynitride over exposed portions of the collector, emitter and base regions of the transistor. This passivation step can be performed using an electron-cyclotron resonance (ECR) plasma to deposit the silicon oxynitride layer.
Additional advantages and novel features of the invention will become apparent to those skilled in the art upon examination of the following detailed description thereof when considered in conjunction with the accompanying drawings. The advantages of the invention can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.